In favor of effective enhancement in electrical and operational performances, it preferably incorporates more than one or a plurality of chips in a single package, thus forming a multi-chip semiconductor package. A conventional multi-chip semiconductor package 1, as shown in FIG. 3, is a substrate-based structure, wherein a first chip 10 is mounted on a substrate 11 and electrically connected thereto by a plurality of first bonding wires 12. A second chip 13 is stacked on the first chip 10, and electrically connected to the substrate 11 by a plurality of second bonding wires 14. An encapsulant 15 is formed on the substrate 11, and encapsulates the first and second chips 10, 13 and the first and second bonding wires 12, 14. A plurality of solder balls 16 are implanted on the substrate 11 opposed in position to the encapsulant 15, and serve as input/output (I/O) ports for electrically connecting the first and second chips 10, 13 to an external device such as a printed circuit board (PCB, not shown). However, this multi-chip semiconductor package 1 is subject to a chip-size limitation problem; that is, the second chip 13 should be smaller in dimension than the first chip 10 so as not to interfere with arrangement of the first bonding wires 12 bonded to the first chip 10.
Accordingly, as shown in FIGS. 4A and 4B, another multi-chip semiconductor package 1′ is provided for solving the above chip-size limitation problem, wherein the second chip 13 is stacked on the first chip 10 in a stagger manner, and thus partly in contact with the first chip 10. By this arrangement, the second chip 13 may be flexibly sized with respect to the first chip 10, and free of concern to interfere with the first bonding wires 12 connected to the first chip 10. However, with partial or incomplete contact between the first and second chips 10, 13, the second chip 13 is formed with at least a suspending portion 130 that lacks support from the first chip 10, with bond pads 131 of the second chip 13, where the second bonding wires 14 are bonded, being situated at the suspending portion 130. During a wire-bonding process for forming the second bonding wires 14, a wire bonder (not shown) exerts a strong force toward the bond pads 131, and thus may lead to cracks of the second chip 13 at the suspending portion 130 that is not supported by the first chip 10.
In response to the above chip-crack problem, a further multi-chip semiconductor package 1″, as shown in FIG. 5, teaches to form a plurality of support members 17 interposed between the suspending portion 130 and the substrate 11. The support members 17 are situated substantially corresponding in position to the bond pads 131 of the second chip 13 where the second bonding wires 14 are bonded, and used to enhance mechanical strength or support for the second chip 13 and at the suspending portion 130. As a result, the second chip 13 may become stronger against the wire-bonding force without easily cracking at the suspending portion 130 during formation of the second bonding wires 14.
However, the above multi-chip semiconductor package 1″ in the use of the support members 17, induces significant problems. One is void or popcorn effect issues; the support members 17 are arranged to undesirably form gaps G between the first chip 10 and the support members 17. During a molding process for forming the chip-encapsulation encapsulant 15 by a resin compound, the relative narrow gaps G would change motion of the resin compound passing therethrough and easily trap air or voids therein; this may lead to popcorn effect with voids left in the encapsulant 15 for the semiconductor package 1″ in subsequent fabrication processes, and thereby adversely affect reliability of fabricated package products.